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1 ltc2424/LTC2428 4-/8-channel 20-bit m power no latency ds tm adcs march 2000 the ltc ? 2424/LTC2428 are 4-/8-channel 2.7v to 5.5v micropower 20-bit a/d converters with an integrated oscillator, 8ppm inl and 1.2ppm rms noise. they use delta-sigma technology and provide single cycle digital filter settling time (no latency delay) for multiplexed applications. the first conversion after the channel is changed is always valid. through a single pin the ltc2424/ LTC2428 can be configured for better than 110db rejec- tion at 50hz or 60hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1hz to 800hz. the internal oscillator requires no external frequency setting components. the converters accept any external reference voltage from 0.1v to v cc . with their extended input conversion range of C12.5% v ref to 112.5% v ref (v ref = fs set C zs set ) the ltc2424/LTC2428 smoothly resolve the offset and overrange problems of preceding sensors or signal con- ditioning circuits. the ltc2424/LTC2428 communicate through a flexible 4-wire digital interface which is compatible with spi and microwire tm protocols. n pin compatible 4-/8-channel 20-bit adcs n 8ppm inl, no missing codes at 20 bits n 4ppm full-scale error and 0.5ppm offset n 1.2ppm noise n digital filter settles in a single cycle. each conversion is accurate, even after changing channels n fast mode: 16-bit noise, 12-bit tue at 100sps n internal oscillatorno external components required n 110db min, 50hz/60hz notch filter n reference input voltage: 0.1v to v cc n live zeroextended input range accommodates 12.5% overrange and underrange n single supply 2.7v to 5.5v operation n low supply current (200 m a) and auto shutdown n can be interchanged with 24-bit ltc2404/ltc2408 if zs set pin is grounded total unadjusted error vs output code , ltc and lt are registered trademarks of linear technology corporation. no latency ds is a trademark of linear technology corporation. microwire is a trademark of national semiconductor corporation. n weight scales n direct temperature measurement n gas analyzers n strain-gage transducers n instrumentation n data acquisition n industrial process control n 4-digit dvms features descriptio u applicatio s u typical applicatio u analog inputs 0.12v ref to 1.12v ref 24248 ta01 ch0 ch1 ch2 ch3 ch4* ch5* ch6* ch7* 9 10 11 12 13 14 15 17 + 4-/8-channel mux 5zs set *these pins are no connects on the ltc2404 gnd 1, 6, 16, 18, 22, 27, 28 mpu serial data link microwire and spi compatable 23 20 25 19 21 24 csadc csmux sck clk d in sdo 26 f o 20-bit ? adc ltc2424/LTC2428 0.1v to v cc adcin muxout 7 4 3 2, 8 1 f 2.7v to 5.5v fs set v cc = internal osc/50hz rejection = external clock source = internal osc/60hz rejection v cc output code (decimal) 0 8,338,608 16,777,215 linearity error (ppm) 24248 ta02 10 8 6 4 2 0 ? ? ? ? ?0 v cc = 5v v ref = 5v t a = 25 c f o = low information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. final electrical specifications
2 ltc2424/LTC2428 order part number consult factory for military grade parts. (notes 1, 2) supply voltage (v cc ) to gnd .......................C 0.3v to 7v analog input voltage to gnd ....... C 0.3v to (v cc + 0.3v) reference input voltage to gnd .. C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) t jmax = 125 c, q ja = 130 c/w ltc2424cg ltc2424ig operating temperature range ltc2424c/LTC2428c .............................. 0 c to 70 c ltc2424i/LTC2428i ........................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number LTC2428cg LTC2428ig t jmax = 125 c, q ja = 130 c/w absolute m axi m u m ratings w ww u package/order i n for m atio n w u u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd v cc fs set adcin zs set gnd muxout v cc ch0 ch1 ch2 ch3 nc nc gnd gnd f o sck sdo csadc gnd d in csmux clk gnd nc gnd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd v cc fs set adcin zs set gnd muxout v cc ch0 ch1 ch2 ch3 ch4 ch5 gnd gnd f o sck sdo csadc gnd d in csmux clk gnd ch7 gnd ch6 parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , (note 5) l 20 bits integral nonlinearity v ref = 2.5v (note 6) l 4 10 ppm of v ref v ref = 5v (note 6) l 8 20 ppm of v ref integral nonlinearity (fast mode) 2.5v < v ref < v cc , 100 samples/second, f o = 2.048mhz l 40 250 ppm of v ref offset error 2.5v v ref v cc l 0.5 10 ppm of v ref offset error (fast mode) 2.5v < v ref < 5v, 100 samples/second, f o = 2.048mhz 3 ppm of v ref offset error drift 2.5v v ref v cc 0.04 ppm of v ref / c full-scale error 2.5v v ref v cc l 4 15 ppm of v ref full-scale error (fast mode) 2.5v < v ref < 5v, 100 samples/second, f o = 2.048mhz 10 ppm of v ref full-scale error drift 2.5v v ref v cc 0.04 ppm of v ref / c the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co n verter characteristics u
3 ltc2424/LTC2428 symbol parameter conditions min typ max units v in input voltage range (note 14) l C 0.125 ? v ref 1.125 ? v ref v v ref reference voltage range l 0.1 v cc v c s(in) input sampling capacitance 1 pf c s(ref) reference sampling capacitance 1.5 pf i in(leak) input leakage current cs = v cc l C100 1 100 na i ref(leak) reference leakage current v ref = 2.5v, cs = v cc l C 100 1 100 na i in(mux) on channel leakage current v s = 2.5v (note 15) l 20 na r on mux on-resistance i out = 1ma, v cc = 2.7v l 250 300 w i out = 1ma, v cc = 5v l 120 250 w mux d r on vs temperature 0.5 %/ c d r on vs v s (note 15) 20 % i s(off) mux off input leakage channel off, v s = 2.5v l 20 na i d(off) mux off output leakage channel off, v d = 2.5v l 20 na t open mux break-before-make interval 290 ns t on enable turn-on time v s = 1.5v, r l = 3.4k, c l = 15pf 490 ns t off enable turn-off time v s = 1.5v, r l = 3.4k, c l = 15pf 190 ns qirr mux off isolation v in = 2v p-p , r l = 1k, f = 100khz 70 db qinj charge injection r s = 0 w , c l = 1000pf, v s = 1v 1pc c s(off) input off capacitance (mux) 10 pf c d(off) output off capacitance (mux) 10 pf the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a d refere ce u u u u parameter conditions min typ max units total unadjusted error v ref = 2.5v 8 ppm of v ref v ref = 5v 16 ppm of v ref output noise v in = 0v, v ref = 5v (note 13) 6 m v rms output noise (fast mode) v ref = 5v, 100 samples/second, f o = 2.048mhz 20 m v rms normal mode rejection 60hz 2% (note 7) l 110 130 db normal mode rejection 50hz 2% (note 8) l 110 130 db power supply rejection, dc v ref = 2.5v, v in = 0v 100 db power supply rejection, 60hz 2% v ref = 2.5v, v in = 0v, (notes 7, 16) 110 db power supply rejection, 50hz 2% v ref = 2.5v, v in = 0v, (notes 8, 16) 110 db the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) co n verter characteristics u
4 ltc2424/LTC2428 symbol parameter conditions min typ max units v ih high level input voltage 2.7v v cc 5.5v l 2.5 v cs, f o 2.7v v cc 3.3v 2.0 v v il low level input voltage 4.5v v cc 5.5v l 0.8 v cs, f o 2.7v v cc 5.5v 0.6 v v ih high level input voltage 2.7v v cc 5.5v (note 9) l 2.5 v sck 2.7v v cc 3.3v (note 9) 2.0 v v il low level input voltage 4.5v v cc 5.5v (note 9) l 0.8 v sck 2.7v v cc 5.5v (note 9) 0.6 v i in digital input current 0v v in v cc l C10 10 m a cs, f o i in digital input current 0v v in v cc (note 9) l C10 10 m a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 9) 10 pf sck v oh high level output voltage i o = C 800 m a l v cc C 0.5v v sdo v ol low level output voltage i o = 1.6ma l 0.4v v sdo v oh high level output voltage i o = C 800 m a (note 10) l v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 10) l 0.4v v sck i oz high-z output leakage l C10 10 m a sdo v in h mux mux high level input voltage v + = 3v l 2v v in l mux mux low level input voltage v + = 2.4v l 0.8 v the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) digital i puts a d digital outputs u u symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current (pin 2) conversion mode cs = 0v (note 12) l 200 300 m a sleep mode cs = v cc (note 12) l 20 30 m a i cc(mux) multiplexer supply current (pin 8) all logic inputs tied together l 15 40 m a v in = 0v or 5v the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) power require e ts w u
5 ltc2424/LTC2428 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) f eosc external oscillator frequency range 20-bit effective resolution l 2.56 307.2 khz 12-bit effective resolution l 2.56k 2.048m hz t heo external oscillator high period l 0.5 390 m s t leo external oscillator low period l 0.5 390 m s t conv conversion time f o = 0v l 130.66 133.33 136 ms f o = v cc l 156.80 160 163.20 ms external oscillator (note 11) l 20480/f eosc (in khz) ms f isck internal sck frequency internal oscillator (note 10) 19.2 khz external oscillator (notes 10, 11) f eosc /8 khz d isck internal sck duty cycle (note 10) 45 55 % f esck external sck frequency range (note 9) l 2000 khz t lesck external sck low period (note 9) l 250 ns t hesck external sck high period (note 9) l 250 ns t dout_isck internal sck 24-bit data output time internal oscillator (notes 10, 12) l 1.23 1.25 1.28 ms external oscillator (notes 10, 11) l 192/f eosc (in khz) ms t dout_esck external sck 24-bit data output time (note 9) l 24/f esck (in khz) ms t 1 cs to sdo low z l 0 150 ns t 2 cs - to sdo high z l 0 150 ns t 3 cs to sck (note 10) l 0 150 ns t 4 cs to sck - (note 9) l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7 to 5.5v unless otherwise specified, source input is 0 w . csadc = csmux = cs. v ref = fs set C zs set . note 4: internal conversion clock source with the f o pin tied to gnd or to v cc or to external conversion clock source with f eosc = 153600hz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f o = 0v (internal oscillator) or f eosc = 153600hz 2% (external oscillator). note 8: f o = v cc (internal oscillator) or f eosc = 128000hz 2% (external oscillator). note 9: the converter is in external sck mode of operation such that the sck pin is used as digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in khz. note 10: the converter is in internal sck mode of operation such that the sck pin is used as digital output. in this mode of operation the sck pin has a total equivalent load capacitance c load = 20pf. note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. f o = 0v or f o = v cc . note 13: the output noise includes the contribution of the internal calibration operations. note 14: for reference voltage values v ref > 2.5v the extended input of C 0.125 ? v ref to 1.125 ? v ref is limited by the absolute maximum rating of the analog input voltage pin (pin 3). for 2.5v < v ref 0.267v + 0.89 ? v cc the input voltage range is C 0.3v to 1.125 ? v ref . for 0.267v + 0.89 ? v cc < v ref v cc the input voltage range is C 0.3v to v cc + 0.3v. note 15: v s is the voltage applied to a channel input. v d is the voltage applied to the mux output. note 16: v cc(dc) = 4.1v, v cc(ac) = 2.8v p-p . ti i g characteristics u w
6 ltc2424/LTC2428 pi n fu n ctio n s uu u gnd (pins 1, 6, 16, 18, 22, 27, 28): ground. should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single-point grounding system. v cc (pins 2, 8): positive supply voltage. 2.7v v cc 5.5v. bypass to gnd with a 10 m f tantalum capacitor in parallel with 0.1 m f ceramic capacitor as close to the part as possible. fs set (pin 3): full-scale set input. this pin defines the full-scale input value. when v in = fs set , the adc outputs full scale (fffff h ). the total reference voltage (v ref ) is fs set C zs set . adcin (pin 4): analog input. the input voltage range is C 0.125 ? v ref to 1.125 ? v ref . for v ref > 2.5v the input voltage range may be limited by the pin absolute maxi- mum rating of C 0.3v to v cc + 0.3v. zs set (pin 5): zero-scale set input. this pin defines the zero-scale input value. when v in = zs set , the adc outputs zero scale (00000 h ). for pin compatibility with the ltc2404/ ltc2408 this pin must be grounded. muxout (pin 7): mux output. this pin is the output of the multiplexer. tie to adcin for normal operation. ch0 (pin 9): analog multiplexer input. ch1 (pin 10): analog multiplexer input. ch2 (pin 11): analog multiplexer input. ch3 (pin 12): analog multiplexer input. ch4 (pin 13): analog multiplexer input. no connect on the ltc2424. ch5 (pin 14): analog multiplexer input. no connect on the ltc2424. ch6 (pin 15): analog multiplexer input. no connect on the ltc2424. ch7 (pin 17): analog multiplexer input. no connect on the ltc2424. clk (pin 19): shift clock for data in. this clock synchro- nizes the serial data transfer into the mux. for normal operation, drive this pin in parallel with sck. csmux (pin 20): mux chip select input. a logic high on this input allows the mux to receive a channel address. a logic low enables the selected mux channel and connects it to the muxout pin for a/d conversion. for normal operation, drive this pin in parallel with csadc. d in (pin 21): digital data input. the multiplexer address is shifted into this input on the last four rising clk edges before csmux goes low. csadc (pin 23): adc chip select input. a low on this pin enables the sdo digital output and following each conver- sion, the adc automatically enters the sleep mode and remains in this low power state as long as csadc is high. a high on this pin also disables the sdo digital output. a low-to-high transition on csadc during the data output state aborts the data transfer and starts a new conversion. for normal operation, drive this pin in parallel with csmux. sdo (pin 24): three-state digital output. during the data output period this pin is used for serial data output. when the chip select csadc is high (csadc = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin can be used as a conversion status output. the conversion status can be observed by pulling csadc low. sck (pin 25): shift clock for data out. this clock synchro- nizes the serial data transfer of the adc data output. data is shifted out of sdo on the falling edge of sck. for normal operation, drive this pin in parallel with clk. f o (pin 26): digital input which controls the adcs notch frequencies and conversion time. when the f o pin is connected to v cc (f o = v cc ), the converter uses its internal oscillator and the digital filter first null is located at 50hz. when the f o pin is connected to gnd (f o = ov), the converter uses its internal oscillator and the digital filter first null is located at 60hz. when f o is driven by an external clock signal with a frequency f eosc , the converter uses this signal as its clock and the digital filter first null is located at a frequency f eosc /2560. the resulting output word rate is f eosc /20480.
7 ltc2424/LTC2428 fu ctio al block diagra uu w test circuits 3.4k sdo 24248 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 3.4k sdo 24248 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc autocalibration and control decimating fir internal oscillator serial interface channel select adc dac gnd 8-channel mux ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 v cc sdo sck fs set zs set csadc f o (int/ext) 24248 bd csmux d in clk applicatio n s i n for m atio n wu u u converter operation cycle the ltc2424/LTC2428 are low power, 4-/8-channel delta- sigma analog-to-digital converters with easy-to-use 4-wire interfaces. their operation is simple and made up of four states. the converter operation begins with the conversion, followed by a low power sleep state and concluded with the data output (see figure 1). channel selection may be performed while the device is in the sleep state or at the conclusion of the data output state. the interface consists of serial data output (sdo), serial clock (clk/sck), chip select (csadc/csmux) and data input (d in ). by tying sck to clk and csadc to csmux, the interface requires only four wires. initially, the ltc2424 or LTC2428 performs a conversion. once the conversion is complete, the device enters the sleep state. while in the sleep state, power consumption is reduced by an order of magnitude. the part remains in the sleep state as long as csadc is logic high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. channel selection for the next conversion cycle is per- formed while the device is in the sleep state or at the end
8 ltc2424/LTC2428 of the data output state. a specific channel is selected by applying a 4-bit serial word to the d in pin on the rising edge of clk while csmux is high, see figure 4 and table 3. the channel is selected based on the last four bits clocked into the d in pin before csmux goes low. if d in is all 0s, the previous channel remains selected. in the example, figure 4, the mux channel is selected during the sleep state, just before the data output state begins. once the channel selection is complete, the device remains in the sleep state as long as csadc remains high. once csadc is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. since there is no latency, the first conversion following a change in input channel is valid and corre- sponds to that channel. the data output corresponds to the conversion just performed. this result is shifted out on the serial data output pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck, see figure 4. the data output state is concluded once 24 bits are read out of the adc or when csadc is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the csadc and sck pins, the ltc2424/LTC2428 offer two modes of operation: internal applicatio n s i n for m atio n wu u u figure 1. LTC2428 state transition diagram convert sleep channel select (sleep) data output (channel select) 24248 f01 0 1 csadc and sck or external sck. these modes do not require program- ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. conversion clock a major advantage delta-sigma converters offer over conventional type converters is an on-chip digital filter (commonly known as sinc or comb filter). for high resolution, low frequency applications, this filter is typi- cally designed to reject line frequencies of 50 or 60hz plus their harmonics. in order to reject these frequencies in excess of 110db, a highly accurate conversion clock is required. the ltc2424/LTC2428 incorporate an on-chip highly accurate oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. clocked by the on-chip oscillator, the ltc2424/ LTC2428 reject line frequencies (50 or 60hz 2%) a minimum of 110db. ease of use the ltc2424/LTC2428 data output has no latency, filter settling or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing an analog input voltage is easy. the ltc2424/LTC2428 perform offset and full-scale cali- brations every conversion cycle. this calibration is trans- parent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2424/LTC2428 automatically enter an internal reset state when the power supply voltage v cc drops below approximately 2.2v. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with duration of approximately 0.5ms. the por signal clears all internal registers within the adc and initiates a conversion. at
9 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u figure 2. ltc2424/LTC2428 input range 24248 f02 v cc + 0.3v 9/8v ref v ref 1/2v ref 0.3v 1/8v ref 0 normal input range extended input range absolute maximum input range power-up, the multiplexer channel is disabled and should be programmed once the device enters the sleep state. the results of the first conversion following a por are not valid since a multiplexer channel was disabled. reference voltage range the ltc2424/LTC2428 can accept a reference voltage from 0v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will not signifi- cantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the overall converter inl performance. the recommended range for the ltc2424/LTC2428 voltage reference is 100mv to v cc . input voltage range the converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range, see figure 2. the ltc2424/LTC2428 converts input signals within the extended input range of C 0.125 ? v ref to 1.125 ? v ref (v ref = fs set C zs set ). for large values of v ref this range is limited to a voltage range of C 0.3v to (v cc + 0.3v). beyond this range the input esd protection devices begin to turn on and the errors due to the input leakage current increase rapidly. input signals applied to v in may extend below ground by C 300mv and above v cc by 300mv. in order to limit any fault current, a resistor of up to 5k may be added in series with any channel input pin (ch0 to ch7) without affecting the performance of the device. in the physical layout, it is im- portant to maintain the parasitic capacitance of the connec- tion between this series resistance and the channel input pin as low as possible; therefore, the resistor should be located as close as practical to the channel input pin. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the analog in- put/reference current section. in addition, a series resis- tor will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. output data format the ltc2424/LTC2428 serial output data stream is 24 bits long. the first 4 bits represent status information indicat- ing the sign, input range and conversion state. the next 20 bits are the conversion result, msb first. the ltc2424/LTC2428 can be interchanged with the ltc2404/ltc2408. the two devices are designed to allow the user to incorporate either device in the same design as long as zs set of the ltc2424/LTC2428 is tied to ground. while the ltc2424/LTC2428 output word lengths are 24 bits (as opposed to the 32-bit output of the ltc2404/ ltc2408), their output clock timing can be identical to the ltc2404/ltc2408. as shown in figure 3, the ltc2424/ ltc2408 data output is concluded on the falling edge of the 24th serial clock (sck). in order to maintain drop-in com- patibility with the ltc2404/ltc2408, it is possible to clock the ltc2424/LTC2428 with an additional 8 serial clock pulses. this results in 8 additional output bits which are always logic high. bit 23 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 22 (second output bit) is a dummy bit (dmy) and is always low. bit 21 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. the sign bit changes state during the zero code.
10 ltc2424/LTC2428 indicating a new conversion cycle has been initiated. this bit serves as eoc (bit 23) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the v in pin is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any input value from C 0.125 ? v ref to 1.125 ? v ref . for input voltages greater than 1.125 ? v ref , the conversion result is clamped to the value corresponding to 1.125 ? v ref . for input voltages below C 0.125 ? v ref , the conversion result is clamped to the value corresponding to C 0.125 ? v ref . channel selection typically, csadc and csmux are tied together or csadc is inverted and drives csmux. sck and clk are tied together and driven with a common clock signal. during channel selection, csmux is high. data is shifted into the d in pin on the rising edge of clk, see figure 4. table 3 shows the bit combinations for channel selection. in order to enable the multiplexer output, csmux must be pulled low. the multiplexer should be programmed after the previous conversion is complete. in order to guarantee the conversion is complete, the multiplexer addressing should be delayed a minimum t conv (approximately 133ms for a 60hz notch) after the data out is read. while the multiplexer is being programmed, the adc is in a low power sleep state. once the mux addressing is complete, the data from the preceding conversion can be read. a new conversion cycle is initiated following the data read cycle with the analog input tied to the newly selected channel. applicatio n s i n for m atio n wu u u bit 20 (forth output bit) is the extended input range (exr) indicator. if the input is within the normal input range 0 v in v ref , this bit is low. if the input is outside the normal input range, v in > v ref or v in < 0, this bit is high. the function of these bits is summarized in table 1. table 1. ltc2424/LTC2428 status bits bit 23 bit 22 bit 21 bit 20 input range eoc dmy sig exr v in > v ref 0 011 0 < v in v ref 0 010 v in = 0 + /0 C 0 0 1/0 0 v in < 0 0 001 bit 19 (fifth output bit) is the most significant bit (msb). bits 19-0 are the 20-bit conversion result msb first. bit 0 is the least significant bit (lsb). data is shifted out of the sdo pin under control of the serial clock (sck), see figure 4. whenever csadc is high, sdo remains high impedance and any sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, csadc must first be driven low. eoc is seen at the sdo pin of the device once csadc is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 23 (eoc) can be captured on the first rising edge of sck. bit 22 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 23rd sck and may be latched on the rising edge of the 24th sck pulse. on the falling edge of the 24th sck pulse, sdo goes high csadc sck sdo conversion sleep 8 8 8 8 (optional) eoc = 1 eoc = 1 last 8 bits always 1 eoc = 0 data out 4 status bits 20 data bits data output 24248 f03 conversion figure 3. ltc2424/LTC2428 compatible timing with the ltc2404/ltc2408
11 ltc2424/LTC2428 table 3. logic table for channel selection channel status en d2 d1 d0 all off 0 x x x ch0 1 0 0 0 ch1 1 0 0 1 ch2 1 0 1 0 ch3 1 0 1 1 ch4* 1 1 0 0 ch5* 1 1 0 1 ch6* 1 1 1 0 ch7* 1 1 1 1 *not used for the ltc2424. applicatio n s i n for m atio n wu u u frequency rejection selection (f o pin connection) the ltc2424/LTC2428 internal oscillator provides better than 110db normal mode rejection at the line frequency and all its harmonics for 50hz 2% or 60hz 2%. for 60hz rejection, f o (pin 26) should be connected to gnd (pin 1) while for 50hz rejection the f o pin should be connected to v cc (pin 2). the selection of 50hz or 60hz rejection can also be made by driving f o to an appropriate logic level. a selection change during the sleep or data output states will not disturb the converter operation. if the selection is made figure 4. typical data input/output timing eoc ? sdo sck/clk d in csmux/csadc msb lsb d2 en d1 d0 ext sig bit 22 bit 23 bit 0 24248 f04 hi-z don? care t conv hi-z table 2. ltc2424/LTC2428 output data format bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15 bit 0 input voltage eoc dmy sig exr msb lsb v in > 9/8 ? v ref 0 0 1100 0 11...1 9/8 ? v ref 0 0 1100 0 11...1 v ref + 1lsb 0 0 1100 0 00...0 v ref 0 0 1011 1 11...1 3/4v ref + 1lsb 0 0 1011 0 00...0 3/4v ref 0 0 1010 1 11...1 1/2v ref + 1lsb 0 0 1010 0 00...0 1/2v ref 0 0 1001 1 11...1 1/4v ref + 1lsb 0 0 1001 0 00...0 1/4v ref 0 0 1000 1 11...1 0 + /0 C 0 0 1/0* 0 0 0 0 0 0 ... 0 C1lsb 0 0 0111 1 11...1 C1/8 ? v ref 0 0 0111 1 00...0 v in < C1/8 ? v ref 0 0 0111 1 00...0 *the sign bit changes state during the 0 code.
12 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u figure 5. ltc2424/LTC2428 normal mode rejection when using an external oscillator of frequency f eosc during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. when a fundamental rejection frequency different from 50hz or 60hz is required or when the converter must be synchronized with an outside source, the ltc2424/ LTC2428 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 2560hz (1hz notch frequency) to be detected. the external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2424/LTC2428 provide better than 110db normal mode rejection in a frequency range f eosc /2560 4% and its harmonics. the normal mode rejection as a function of the input frequency deviation from f eosc /2560 is shown in figure 5. whenever an external clock is not present at the f o pin the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2424/LTC2428 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside specifications but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 4 summarizes the duration of each state as a function of f o . input frequency deviation from notch frequency (%) 128404812 rejection (db) 24248 f05 ?0 ?0 ?0 ?0 100 110 120 130 140 table 4. ltc2424/LTC2428 state duration state operating mode duration convert internal oscillator f o = low (60hz rejection) 133ms f o = high (50hz rejection) 160ms external oscillator f o = external oscillator 20480/f eosc (in seconds) with frequency f eosc khz (f eosc /2560 rejection) sleep as long as csadc = high until csadc = 0 and sck data output internal serial clock f o = low/high as long as csadc = low but not longer than 1.67ms (internal oscillator) (32 sck cycles) f o = external oscillator with as long as csadc = low but not longer than 256/f eosc ms frequency f eosc khz (32 sck cycles) external serial clock with as long as csadc = low but not longer than 32/f sck ms frequency f sck khz (32 sck cycles) maximum output word rate (owr) owr tt in hz convert dataoutput = + 1
13 ltc2424/LTC2428 data rate with a 5v reference. the relationship between the output data rate (odr) and the frequency applied to the f o pin (f o ) is: odr = f o /20480 for output data rates up to 50 samples/second, the total unadjusted error (tue) is better than 16 bits, and better than 12 bits at 100 samples/second. as shown in figure 8, for output data rates of 100 samples/second, the tue is better than 15 bits for v ref below 2.5v. figure 9 shows an unaveraged total unadjusted error for the ltc2424 or LTC2428 operating at 100 samples/second with v ref = 2.5v. figure 10 shows the same device operating with a 5v reference and an output data rate of 7.5 samples/second. operation at higher data output rates the ltc2424/LTC2428 typically operate with an internal oscillator of 153.6khz. this corresponds to a notch fre- quency of 60hz and an output rate of 7.5 samples/second. the internal oscillator is enabled if the f o pin is logic low (logic high for a 50hz notch). it is possible to drive the f o pin with an external oscillator for higher data output rates. as shown in figure 6, an external clock of 2.048mhz applied to the f o pin results in a notch frequency of 800hz with a data output rate of 100 samples/second. figure 7 shows the total unadjusted error (offset error + full-scale error + inl + dnl) as a function of the output applicatio n s i n for m atio n wu u u output rate (samples/sec) 0 total unadjusted error (ppm) 96 128 160 12 bits 13 bits 14 bits 16 bits 24248 f07 64 32 0 50 100 192 224 256 v ref = 5v 150 figure 7. total error vs output rate (v ref = 5v) ltc2424 c9 0.1 f hco4 hco4 c7 10pf c6 270pf c8 5pf r7 5k r6 47k r8 1k 10k 10 tven pot switch r9 1k 5v 6 12 10 5 7 3 4 21 13 11 89 24248 f06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd v cc fs set adcin zs set gnd muxout v cc ch0 ch1 ch2 ch3 nc nc gnd gnd f o sck sdo csadc gnd d in csmux clk gnd nc gnd nc + figure 6. selectable 100 sample/second turbo mode reference voltage (v) 1.0 total unadjusted error (ppm) 128 192 5.0 24248 f08 64 0 2.0 3.0 4.0 1.5 2.5 3.5 4.5 256 96 160 32 224 output rate = 100sps 12 bits 13 bits 14 bits 15 bits figure 8. total error vs v ref (output rate = 100sps) input voltage (v) 0 ?0 total unadjusted error (ppm) ?0 ?5 ?0 ?5 ?0 ? 24248 f09 0 5 10 ?5 2.5 v cc = 5v v ref = 2.5v figure 9. total unadjusted error at 100 samples/second (no averaging)
14 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u at 100 samples/second, the ltc2424/LTC2428 can be used to capture transient data. this is useful for monitor- ing settling or auto gain ranging in a system. the ltc2424/ LTC2428 can monitor signals at an output rate of 100 samples/second. after acquiring 100 samples/second data, the f o pin may be driven low enabling 60hz rejection to 110db and the highest possible dc accuracy. the no latency architecture of the ltc2424/LTC2428 allows con- secutive readings (one at 100 samples/second the next at 7.5 samples/second) without interaction between the two readings. as shown in figure 11, the ltc2424/LTC2428 can cap- ture transient data with 90db of dynamic range (with a input voltage (v) 0 total unadjusted error (ppm) ? 0 2 5 24248 f10 ? ? ?0 ? 6 4 v cc = 5v v ref = 5v figure 10. total unadjusted error at 7.5 samples/second (no averaging) 300mv p-p input signal at 2hz). the exceptional dc performance of the ltc2424/LTC2428 enables signals to be digitized independent of a large dc offset. figures 12a and 12b show the dynamic performance with a 15hz signal superimposed on a 2v dc level. the same signal with no dc level is shown in figures 12c and 12d. serial interface the ltc2424/LTC2428 transmit the conversion results, program the channel selection, and receive the start of conversion command through a synchronous 4-wire in- terface (sck = clk, csadc = csmux). during the conver- sion and sleep states, this interface can be used to assess the converter status. while in the sleep state this interface may be used to program an input channel. during the data output state, it is used to read the conversion result. adc serial clock input/output (sck) the serial clock signal present on sck (pin 25) is used to synchronize the data transfer. each bit of data is shifted out of the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2424/LTC2428 creates its own serial clock by dividing the internal conversion clock by 8. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected on power-up and then reselected every time a high-to-low transition is detected at the csadc pin. if sck is high or 0.5 1 1.5 2 2.5 time (sec) adc output (normalized to volts) 0 0.05 0.10 24248 f11a 0.05 0.10 0.20 0.15 0.20 500ms 0.15 f in = 2hz magnitude (db) ?0 ?0 ?0 0 ?0 100 120 2hz 100sps 0v offset 24248 f11b frequency (hz) 25 50 0 figure 11b. output fft figure 11a. digitized waveform figure 11. transient signal acquisition
15 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u figure 12. using the ltc2424/LTC2428s high accuracy wide dynamic range to digitize a 300mv p-p 15hz waveform with a large dc offset (v cc = 5v, v ref = 5v) 1.5 2 2.5 0.5 1 time (sec) adc output (normalized to volts) 2.00 2.05 2.10 24248 f12a 1.95 1.90 1.80 1.85 2.20 2.15 v in = 300mv p-p + 2v dc 25 50 0 frequency (hz) magnitude (db) ?0 ?0 ?0 0 24248 f12b ?0 100 120 15hz 100sps 2v offset 1.5 2 2.5 1 0.5 time (sec) adc output (normalized to volts) 0.00 0.05 0.10 24248 f12c 0.05 0.10 0.20 0.15 0.20 0.15 v in = 300mv p-p + 0v dc 25 50 0 frequency (hz) magnitude (db) ?0 ?0 ?0 0 24248 f12d ?0 100 120 15hz 100sps 0v offset figure 12b. fft waveform with 2v dc offset figure 12a. digitized waveform with 2v dc offset figure 12d. fft waveform with no offset figure 12c. digitized waveform with no offset floating at power-up or during this transition, the converter enters the internal sck mode. if sck is low at power-up or during this transition, the converter enters the external sck mode. multiplexer serial input clock (clk) generally, this pin is externally tied to sck for 4-wire op- eration. on the rising edge of clk (pin 19) with csmux held high, data is serially shifted into the multiplexer. if csmux is low the clk input will be disabled and the channel selection unchanged. serial data output (sdo) the serial data output pin, sdo (pin 24), drives the serial data during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when csadc (pin 23) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if csadc is low during the convert or sleep state, sdo will output eoc. if csadc is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while csadc = 0. adc chip select input (csadc) the active low chip select, csadc (pin 23), is used to test the conversion status and to enable the data output transfer as described in the previous sections.
16 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u in addition, the csadc signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2424/LTC2428 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the csadc pin after the converter has entered the data output state (i.e., after the first rising edge of sck occurs with csadc = 0). multiplexer chip select (csmux) for 4-wire operation, this pin is tied directly to csadc or the output of an inverter tied to csadc. csmux (pin 20) is driven high during selection of a multiplexer channel. on the falling edge of csmux, the selected channel is enabled and drives muxout. data input (d in ) the data input to the multiplexer, d in (pin 21), is used to program the multiplexer. the input channel is selected by serially shifting a 4-bit input word into the d in pin under the control of the multiplexer clock, clk. data is shifted into the multiplexer on the rising edge of clk. table 3 shows the logic table for channel selection. in order to select or change a previously programmed channel, an enable bit (d in = 1) must proceed the 3-bit channel select serial data. the user may set d in = 0 to continually convert on the previously selected channel. serial interface timing modes the ltc2424/LTC2428s 4-wire interface is spi and microwire compatible. this interface offers two modes of operation. these include an internal or external serial clock. the following sections describe both of these serial interface timing modes in detail. for both cases the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 5 for a summary. external serial clock (spi/microwire compatible) this timing mode uses an external serial clock (sck) to shift out the conversion result, see figure 13. this same external clock signal drives the clk pin in order to pro- gram the multiplexer. a single cs signal drives both the multiplexer csmux and converter csadc inputs. this common signal is used to monitor and control the state of the conversion as well as enable the channel selection. the serial clock mode is selected on the falling edge of csadc. to select the external serial clock mode, the serial clock pin (sck) must be low during each csadc falling edge. the serial data output pin (sdo) is hi-z as long as csadc is high. at any time during the conversion cycle, csadc may be pulled low in order to monitor the state of the converter. while csadc is low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of csadc, the device automatically enters the low power sleep state once the conversion is complete. while the device is in the sleep state, prior to entering the data output state, the user may program the multiplexer. as shown in figure 13, the multiplexer channel is selected by serial shifting a 4-bit word into the d in pin on the rising edge of clk (clk is tied to sck). the first bit is an enable bit that must be high in order to program a channel. the next three bits determine which channel is selected, see table 3. on the falling edge of csmux, the new channel is selected and will be valid for the first conversion performed following the data output state. clock signals applied to the clk pin while csmux is low (during the data output state) will have no effect on the channel selection. further- more, if d in is held low or clk is held low during the sleep state, the channel selection is unchanged. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis ter. table 5. ltc2424/LTC2428 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck external csadc and sck csadc and sck figures 7, 8, 9 internal sck internal csadc csadc figures 10, 11
17 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u the device remains in the sleep state until the first rising edge of sck is seen while csadc is low. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 24th rising edge of sck. on the 24th falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) indicating a conversion is in progress. at the conclusion of the data cycle, csadc may remain low and eoc monitored as an end-of-conversion inter- rupt. alternatively, csadc may be driven high setting sdo to hi-z. as described above, csadc may be pulled low at any time in order to monitor the conversion status. for each of these operations, csmux may be tied to csadc without affecting the selected channel. at the conclusion of the data output cycle, the converter enters a user transparent calibration cycle prior to actually performing a conversion on the selected input channel. this enables a 66ms (for 60hz notch frequency) look ahead time for the multiplexer input. following the data output cycle, the multiplexer input channel may be selected any time in this 66ms window by pulling csadc high and serial shifting data into the d in pin, see figure 14. while the device is performing the internal calibration, it is sensitive to ground current disturbances. error currents flowing in the ground pin may lead to offset errors. if the sck pin is toggling during the calibration, these ground disturbances will occur. the solution is to either drive the multiplexer clock input (clk) separately from the adc clock input (sck), or program the multiplexer in the first 1ms following the data output cycle. the remaining 65ms may be used to allow the input signal to settle. typically, csadc remains low during the data output state. however, the data output state may be aborted by pulling csadc high anytime between the first rising edge and the 24th falling edge of sck, see figure 15. on the rising edge of csadc, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. internal serial clock this timing mode uses an internal serial clock to shift out the conversion result and program the multiplexer, see figure 16. a cs signal directly drives the csadc input, while the inverse of cs drives the csmux input. the cs sck/clk sdo d in csadc/ csmux v cc f o fs set csmux csadc sck clk muxout adcin d in zs set gnd sdo 0.1v to v cc ch0 to ch7 0.12v ref to 1.12v ref 2.7v to 5.5v ltc2424/LTC2428 msb exr sig bit0 lsb bit4 bit19 bit18 bit20 bit21 bit22 bit23 24248 f13 = 50hz rejection = external oscillator = 60hz rejection v cc test eoc don? care don? care en d2 d1 d0 hi-z hi-z test eoc hi-z test eoc cs sck figure 13. external serial clock timing diagram
18 ltc2424/LTC2428 figure 15. external serial clock with reduced data output length timing diagram sck/clk sdo d in csadc/ csmux v cc cs sck f o fs set csmux csadc sck clk muxout adcin d in zs set gnd sdo 0.1v to v cc ch0 to ch7 0.12v ref to 1.12v ref 2.7v to 5.5v ltc2424/LTC2428 msb exr sig bit8 bit9 bit19 bit18 bit20 bit21 bit22 bit23 24248 f15 = 50hz rejection = external oscillator = 60hz rejection v cc test eoc don? care don? care en d2 d1 d0 hi-z hi-z test eoc applicatio n s i n for m atio n wu u u signal is used to monitor and control the state of the conversion cycles as well as enable the channel selection. the multiplexer is programmed during the data output state. the internal serial clock (sck) generated by the adc is applied to the multiplexer clock input (clk). in order to select the internal serial clock timing mode, the serial clock pin (sck) must be floating (hi-z) or pulled high prior to the falling edge of csadc. the device will not enter the internal serial clock mode if sck is driven low on the falling edge of csadc. an internal weak pull-up resistor is active on the sck pin during the falling edge of csadc; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as csadc is high. at any time during the conversion cycle, csadc may be pulled low in order to monitor the state of the converter. once csadc is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. figure 14. use of look ahead to program multiplexer after data output sck/clk sdo converter state d in csadc/ csmux msb exr sig bit0 lsb bit4 bit19 bit18 bit20 bit21 bit22 bit23 24248 f14 test eoc conv sleep data output internal calibration 66ms look ahead conversion on selected channel don? care don? care en d2 d1 d0 hi-z test eoc 66ms convert 133ms conversion cycle (output rate = 7.5hz)
19 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u figure 16. internal serial clock timing diagram sckclk sdo d in csadc csmux t eoctest msb lsb exr sig bit0 bit4 bit3 bit2 bit1 bit19 bit18 bit20 bit21 bit22 bit23 24248 f16 test eoc don? care don? care en d2 d1 d0 hi-z hi-z hi-z test eoc test eoc v cc cs 10k f o fs set csmux csadc sck clk muxout adcin gnd d in zs set sdo 0.1v to v cc ch0 to ch7 0.12v ref to 1.12v ref 2.7v to 5.5v ltc2424/LTC2428 = 50hz rejection = external oscillator = 60hz rejection v cc when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if csadc remains low. in order to prevent the device from exiting the low power sleep state, csadc must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of csadc (if eoc = 0) or t eoctest after eoc goes low (if csadc is low during the falling edge of eoc). the value of t eoctest is 23 m s if the device is using its internal oscillator (f 0 = logic low or high). if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc . if csadc is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. if csadc remains low longer than t eoctest , the first rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins on this first rising edge of sck and concludes after the 24th rising edge. data is shifted out the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the first rising edge of sck and the last bit of the conversion result on the 24th rising edge of sck. after the 24th rising edge, sdo goes high (eoc = 1), sck stays high, and a new conversion starts. while operating in the internal serial clock mode, the sck output of the adc may be used as the multiplexer clock (clk). d in is latched into the multiplexer on the rising edge of clk. as shown in figure 16, the multiplexer channel is selected by serial shifting a 4-bit word into the d in pin on the rising edge of clk. the first bit is an enable bit which must be high in order to program a channel. the next three bits determine which channel is selected, see table 3. on the rising edge of csadc (falling edge of csmux), the new channel is selected and will be valid for the next conversion. if d in is held low during the data output state, the previous channel selection remains valid.
20 ltc2424/LTC2428 figure 17. internal serial clock with reduced data output length timing diagram sckclk sdo d in csadc csmux t eoctest msb exr sig bit8 bit12 bit11 bit10 bit9 bit19 bit18 bit20 bit21 bit22 bit23 24248 f17 test eoc don? care don? care en d2 d1 d0 hi-z hi-z hi-z test eoc test eoc v cc cs 10k f o fs set csmux csadc sck clk muxout adcin gnd d in zs set sdo 0.1v to v cc ch0 to ch7 0.12v ref to 1.12v ref 2.7v to 5.5v ltc2424/LTC2428 = 50hz rejection = external oscillator = 60hz rejection v cc applicatio n s i n for m atio n wu u u typically, csadc remains low during the data output state. however, the data output state may be aborted by pulling csadc high anytime between the first and 24th rising edge of sck, see figure 17. on the rising edge of csadc, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if csadc is pulled high while the con- verter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of csadc. this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling csadc high when sck is low. whenever sck is low, the ltc2424/LTC2428s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an exter- nal driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2424/LTC2428s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of csadc, the device is switched to the external sck timing mode. by adding an external 10k pull- up resistor to sck, this pin goes high once the external driver goes hi-z. on the next csadc falling edge, the device will remain in the internal sck timing mode. a similar situation may occur during the sleep state when csadc is pulsed high-low-high in order to test the conversion status. if the device is in the sleep state (eoc = 0), sck will go low. once csadc goes high (within the time period defined above as t eoctest ), the internal pull-up is activated. for a heavy capacitive load on the sck pin, the internal pull-up may not be adequate to return sck to a high level before csadc goes low again. this is not a concern under normal conditions
21 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u where csadc remains low after detecting eoc = 0. this situation is easily avoided by adding an external 10k pull- up resistor to the sck pin. digital signal levels the ltc2424/LTC2428s digital interface is easy to use. its digital inputs (f o , csadc, csmux, clk, d in and sck in external sck mode of operation) accept standard ttl/ cmos logic levels and can tolerate edge rates as slow as 100 m s. however, some considerations are required to take advantage of exceptional accuracy and low supply current. the digital output signals (sdo and sck in internal sck mode of operation) are less of a concern because they are not generally active during the conversion state. in order to preserve the accuracy of the ltc2424/LTC2428, it is very important to minimize the ground path imped- ance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. the zs set pin (pin 6) should be con- nected directly to the signal ground. the power supply current during the conversion state should be kept to a minimum. this is achieved by restrict- ing the number of digital signal transitions occurring during this period. while a digital input signal is in the 0.5v to (v cc C 0.5v) range, the cmos input receiver draws additional current from the power supply. it should be noted that, when any one of the digital input signals (f o , csadc, csmux, d in , clk and sck in external sck mode of operation) is within this range, the ltc2424/LTC2428 power supply current may increase even if the signal in question is at a valid logic level. for micropower operation and in order to minimize the potential errors due to additional ground pin current, it is recommended to drive all digital input signals to full cmos levels [v il < 0.4v and v oh > (v cc C 0.4v)]. severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. under- shoot and overshoot can occur because of the imped- ance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to ltc2424/LTC2428. for reference, on a regular fr-4 board, signal propaga- tion velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. thus, a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. this problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. the solution is to carefully terminate all transmission lines close to their characteristic impedance. parallel termination near the ltc2424/LTC2428 input pins will eliminate this problem but will increase the driver power dissipation. a series resistor between 27 w and 56 w placed near the driver or near the ltc2424/LTC2428 pin will also eliminate this problem without additional power dissipation. the actual resistor value depends upon the trace impedance and connection topology. driving the input and reference the analog input and reference of the typical delta-sigma analog-to-digital converter are applied to a switched ca- pacitor network. this network consists of capacitors switch- ing between the analog input (adcin), zs set (pin 6) and the reference (fs set ). the result is small current spikes seen at both adcin and v ref . a simplified input equivalent circuit is shown in figure 18. the key to understanding the effects of this dynamic input current is based on a simple first order rc time constant model. using the internal oscillator, the internal switched capacitor network of the ltc2424/LTC2428 is clocked at 153,600hz corresponding to a 6.5 m s sampling period. fourteen time constants are required each time a capacitor is switched in order to achieve 1ppm settling accuracy. therefore, the equivalent time constant at v in and v ref should be less than 6.5 m s/14 = 460ns in order to achieve 1ppm accuracy. input current (v in ) if complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. if the settling is incomplete, it does not degrade the linearity performance of the device. it simply results in an offset/
22 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u full-scale shift, see figure 19. to simplify the analysis of input dynamic current, two separate cases are assumed: large capacitance at v in (c in > 0.01 m f) and small capaci- tance at v in (c in < 0.01 m f). if the total capacitance at v in (see figure 20) is small (< 0.01 m f), relatively large external source resistances (up to 20k for 20pf parasitic capacitance) can be tolerated without any offset/full-scale error. antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2424/LTC2428 signifi- cantly simplify antialiasing filter requirements. the digital filter provides very high rejection except at integer multiples of the modulator sampling frequency (f s ), see figure 21. the modulator sampling frequency is 256 ? f o , where f o is the notch frequency (typically 50hz or 60hz). the bandwidth of signals not rejected by the digital filter is narrow ( ? 0.2%) compared to the bandwidth of the frequencies rejected. figure 18. ltc2424/LTC2428 equivalent analog input circuit fs set chx adcv cc (pin 2) r sw 5k average input current: i dc = 0.25(v in ?0.5 ?v ref ) ?f ?c eq i ref i ref adcv cc (pin 2) i in(leak) i in(leak) i dc muxv cc (pin 8) i in(mux) i in(mux) r sw 5k r sw 75 c eq 1pf (typ) r sw 5k selected channel 24248 f18 f out = 50hz, internal oscillator: f = 128khz f out = 60hz, internal oscillator: f = 153.6khz external oscillator: 2.56khz f 307.2khz zs set adcin muxout figure 19. offset/full-scale shift figure 20. an rc network at ch0 to ch7 0 tue v ref /2 v in 24248 f19 v ref c in 24248 f20 intput signal source r source ch0 to ch7 ltc2424/ LTC2428 c par @ 20pf figure 21. sync 4 filter rejection input frequency 0 ?0 ?0 0 24248 f21 ?0 100 f s /2 f s 120 140 ?0 rejection (db)
23 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u as a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the ltc2424/LTC2428. if passive rc components are placed in front of the ltc2424/LTC2428, the input dy- namic current should be considered. in cases where large effective rc time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current. the modulator contained within the ltc2424/LTC2428 can handle large-signal level perturbations without satu- rating. signal levels up to 40% of v ref do not saturate the analog modulator. these signals are limited by the input esd protection to 300mv below ground and 300mv above v cc . the LTC2428s resolution and accuracy allows you to measure points in a ladder of sensors in many industrial processes, for example, cracking tow- ers in petroleum refineries, a group of temperature mea- surements must be related to one another. a series of platinum rtds that sense slow changing temperatures can be configured into a resistive ladder, using the LTC2428 to sense each node. this approach allows a single excita- tion current passed through the entire ladder, reducing total supply current consumption. in addition, this ap- proach requires only one high precision resistor, thereby reducing cost. a group of up to seven temperatures can be measured as a group by a single LTC2428 in a loop-pow- ered remote acquisition unit. in the example shown in figure 22, the excitation current is 240 m a at 0 c. the LTC2428 requires 300 m a, leaving nearly 3.5ma for the remainder of the remote transmitter. the resistance of any of the rtds (pt1 to pt7) is deter- mined from the voltage across it, as compared to the voltage drop across the reference resistor (r1). this is a ratiometric implementation where the voltage drop across r1 is given by v ref C v ch1 . channel 7 is used to measure the voltage on a representative length of wire. if the same type and length of wire is used for all connections, then errors associated with the voltage drops across all wiring can be removed in software. the contribution of wiring drop can be scaled if wire lengths are not equal. figure 22. measuring up to seven rtd temperatures with one reference resistor and one reference current 24248 f22 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 9 10 11 12 13 14 15 17 8-channel mux 5zs set gnd 1, 6, 16, 18, 22, 27, 28 23 20 25 19 21 24 csadc csmux sck clk d in sdo 26 f o LTC2428 adcin muxout 74 7 0.1 f 6 3 6 47 f r2 300 a 5v 45 optional gain block 2 to pt3-pt6 pt1 100 platinum rtd optional protection resistors 5k max up to several hundred feet. all same wire type pt2 pt7 4 r3 5v r2 r1 20.1k 0.1% 3 2, 8 1 f 5v fs set v cc v cc + + ltc1050 ltc1634-2.5 + 20-bit ? adc
24 ltc2424/LTC2428 gain can be added to this circuit as the total voltage drop across all the rtds is small compared to adc full-scale range. the maximum recommended gain is 50, as limited by both amplifier noise contribution, as well as the maxi- mum voltage developed at ch0 when all sensors are at the maximum temperature specified for platinum rtds. adding gain requires that one of the resistors (pt1 to pt7) be a precision resistor in order to eliminate the error asso- ciated with the gain setting resistors r2 and r3. note, that if a precision (100 w to 400 w ) resistor is used in place of one of the rtds (pt7 recommended), r1 does not need to be a high precision resistor. although the substitution of a precision reference resistor for an rtd to determine gain may suggest that r2 and r3 (and r1) need not be precise, temperature fluctuations due to airflow may ap- pear as noise that cannot be removed in firmware. conse- quently, these resistors should be low temperature coef- ficient devices. the use of higher resistance rtds is not recommended in this topology, although the inclusion of one 1000 w rtd at the top on the ladder will have minimal impact on the lower elements. the same caveat applies to fast changing temperatures. any fast changing sensors should be at the top of the ladder. the LTC2428s uncommitted multiplexer finds use in a programmable gain scheme if the multiplexer in the LTC2428 is not committed to channel selection, it can be used to select various signal- processing options such as different gains, filters or at- tenuator characteristics. in figure 23, the multiplexer is shown selecting different taps on an r/2r ladder in the feedback loop of an amplifier. this example allows selec- tion of gain from 1 to 128 in binary steps. other feedback networks could be used to provide gains tailored for specific purposes. (for example, 1x, 1.1x, 1.41x, 2x, 2.028x, 5x, 10x, 40x, etc.) alternatively, different bandpass characteristics or signal inversion/noninversion could be selected. the r/2r ladder can be purchased as a network to ensure tight temperature tracking. alternatively, resis- tors in a ladder or as separate dividers can be assembled from discrete resistors. in the configuration shown, the channel resistance of the multiplexer does not contribute much to the error budget, as only input op amp current applicatio n s i n for m atio n wu u u flows through the switch. the ltc1050 was chosen for its low input current and offset voltage, as well as its ability to drive the input of a ds adc. insert gain or buffering after the multiplexer separate muxout and adcin terminals permit insertion of a gain stage between the mux and the adc. if passive filtering is used at the input to the adc, a buffer amplifier is strongly recommended to avoid errors resulting from the dynamic adc input current. if antialiasing is required, it should be placed at the input to the mux. if bandwidth limiting is required to improve noise performance, a filter with a C3db point at 1500hz will reduce the effective total noise bandwidth of the system to 15hz. a roll-off at 1500hz eliminates all higher order images of the base bandwidth of 6hz. in the example shown, the optional bandwidth- limit ing filter has a C 3db point at 1450hz. this filter can be inserted after the multiplexer provided that higher source impedance prior to the multiplexer does not reduce the C 3db frequency, extending settling time, and resulting in charge sharing between samples. the settling time of this filter to 20+ bits of accuracy is less than 2ms. in the pres- ence of external wideband noise, this filter reduces the apparent noise by a factor of 5. note that the noise band- width for noise developed in the amplifier is 150hz. in the example shown, the gain of the amplifier is set to 40, the point at which amplifier noise gain dominates the LTC2428 noise. input voltage range as shown is then 0v to 125mv dc. the recommended capacitor at c2 for a gain of 40 would be 560pf. an 8-channel dc-to-daylight digitizer the circuit in figure 25 shows an example of the LTC2428s flexibility in digitizing a number of real-world physical phenomenafrom dc voltages to ultraviolet light. all of the examples implement single-ended signal condition- ing. although differential signal conditioning is a pre- ferred approach in applications where the sensor is a bridge-type, is located some distance from the adc or operates in a high ambient noise environment, the LTC2428s low power dissipation allows circuit operation in close prox imity to the sensor. as a result, conditioning the sensor output can be greatly simplified through the
25 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u figure 23. using the multiplexer to produce programmable gains of 1 to 128 figure 24. inserting gain between the multiplexer and the adc input 24248 f23 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 9 10 11 12 13 14 15 17 8-channel mux 5zs set gnd 1, 6, 16, 18, 22, 27, 28 23 20 25 19 21 24 csadc csmux sck clk d in sdo 26 f o LTC2428 adcin muxout 74 6 2 4 8 16 32 64 128 av = 1, 2, 4...128 3 v in 2 5v 10k 10k 20k 10k 20k 10k 20k 10k 20k 10k 20k 10k 20k 10k 20k 3 2, 8 1 f 5v fs set v cc v cc + ltc1050 0.1v to v cc + 20-bit ? adc 24248 f24 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 9 10 11 12 13 14 15 17 8-channel mux 5 analog inputs zs set gnd 1, 6, 16, 18, 22, 27, 28 23 20 25 19 21 24 csadc csmux sck clk d in sdo 26 f o LTC2428 adcin muxout 74 7 6 3 c1 0.022 f 2 4 r3 200k c2 optional gain and roll-off optional bandwidth limit 5v r2 5.1k 3 2, 8 10 f 5v fs set v cc v cc r4 5k may be required by other amplifiers (is required by bipolar amplifiers) r1 5.1k + ltc1050 + 20-bit ? adc
26 ltc2424/LTC2428 use of single-ended arrangements. in those applications where differential signal conditioning is required, chopper amplifier-based or self-contained instrumentation ampli- fiers (also available from ltc) can be used with the LTC2428. with the resistor network connected to ch0, the LTC2428 is able to measure dc voltages from 1mv to 1kv in a single range without the need for autoranging. the 990k resistor should be a 1w resistor rated for high voltage operation. alternatively, the 990k resistor can be replaced with a series connection of several lower cost, lower power metal film resistors. the circuit connected to ch1 shows an lt1793 fet input operational amplifier used as an electrometer for high impedance, low frequency applications such as measur- ing ph. the circuit has been configured for a gain of 21; thus, the input signal range is C15mv v in 250mv. an amplifier circuit is necessary in these applications be- cause high output impedance sensors cannot drive switched-capacitor adcs directly. the lt1793 was cho- sen for its low input bias current (10pa, max) and low noise (8nv/ ? hz) performance. as shown, the use of a driven guard (and teflon tm standoffs) is recommended in high impedance sensor applications; otherwise, pc board surface leakage current effects can degrade results. the circuit connected to ch2 illustrates a precision half- wave rectifier that uses the LTC2428s internal ds adc as an integrator. this circuit can be used to measure 60hz, 120hz or from 400hz to 1khz with good results. the LTC2428s internal sinc 4 filter effectively eliminates any frequency in this range. above 1khz, limited amplifier gain-bandwidth product and transient overshoot behavior can combine to degrade performance. the circuits dy- namic range is limited by operational amplifier input offset voltage and the systems overall noise floor. using an ltc1050 chopper-stabilized operational amplifier with a v os of 5 m v, the dynamic range of this application covers approximately 5 orders of magnitude. the circuit configu- ration is best implemented with a precision, 3-terminal, 2-resistor 10k w network (for example, an irc pfc-d network) for r6 and r7 to maintain gain and temperature stability. alternatively, discrete resistors with 0.1% initial applicatio n s i n for m atio n wu u u tolerance and 5ppm/ c temperature coefficient would also be adequate for most applications. two channels (ch3 and ch4) of the LTC2428 are used to accommodate a 3-wire 100 w , pt rtd in a unique circuit that allows true rms/rf signal power measurement from audio to gigahertz (ghz) frequencies. the unique feature of this circuit is that the signal power dissipated in the 50 w termination in the form of heat is measured by the 100 w rtd. two readings are required to compensate for the rtds lead-wire resistance. the reading on ch4 is multi- plied by 2 and subtracted from the reading on ch3 to determine the exact value of the rtd. while the LTC2428 is capable of measuring signals over a range of five decades, the implementation (mechanical, electrical and thermal) of this technique ultimately deter- mines the performance of the circuit. the thermal resis- tance of the assembly (the 50 w /rtd mass to its enclosure) will determine the sensitivity of the circuit. the dynamic range of the circuit will be determined by the maximum temperature the assembly is rated to withstand, approxi- mately 850 c. details of the implementation are quite involved and are beyond the scope of this document. please contact ltc directly for a more comprehensive treatment of this implementation. in the circuit connected to the LTC2428s ch5 input, a thermistor is configured in a half-bridge arrangement that could be used to measure the case temperature of the rtd-based thermal power measurement scheme described previously. in general, thermistors yield very good resolu- tion over a limited temperature range. for the half-bridge arrangement shown, the LTC2428 can measure tempera- ture changes over nearly 5 orders of magnitude. connected to the LTC2428s ch6 input, an infrared ther- mocouple (omega engineering os36-1) can be used in limited range, noncontact temperature measurement ap- plications or applications where high levels of infrared light must be measured. given the LTC2428s 1.2ppm rms noise performance, measurement resolution using infra- red thermocouples is approximately 0.25 cequivalent to the resolution of a conventional type j thermocouple. teflon is a trademark of dupont company.
27 ltc2424/LTC2428 applicatio n s i n for m atio n wu u u these infrared thermocouples are self-contained: 1) they do not require external cold junction compensation; 2) they cannot use conventional open thermocouple detec- tion schemes; and 3) their output impedances are high, approximately 3k w . alternatively, conventional thermo- couples can be connected directly to the LTC2428 (not shown) and cold junction compensation can be provided by an external temperature sensor connected to a different channel (see the thermistor circuit on ch5) or by using the lt1025, a monolithic cold-junction compensator ic. the components connected to ch7 are used to sense daylight or photodiode current with a resolution of 300pa. in the figure, the photodiode is biased in photoconduc- tive mode; however, the LTC2428 can accommodate either photovoltaic or photoconductive configurations. the photodiode chosen (hammatsu s1336-5bk) pro- duces an output of 500ma per watt of optical illumination. the output of the photodiode is dependent on two factors: active detector area (2.4mm ? 2.4mm) and illumination intensity. with the 5k resistor, optical intensities up to 368w/m 2 at 960nm (direct sunlight is approximately 1000w/m 2 ) can be measured by the LTC2428. with a resolution of 1na, the optical dynamic range covers 5 orders of magnitude. the application circuits shown connected to the LTC2428 demonstrate the mix-and-match capabilities of this multi- plexed-input, high resolution ds adc. very low level signals and high level signals can be accommodated with a minimum of additional circuitry. dimensions in millimeters (inches) unless otherwise noted. package descriptio u g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g28 ssop 1098 0.13 ?0.22 (0.005 ?0.009) 0 ?8 0.55 ?0.95 (0.022 ?0.037) 5.20 ?5.38** (0.205 ?0.212) 7.65 ?7.90 (0.301 ?0.311) 1234 5 6 7 8 9 10 11 12 14 13 10.07 ?10.33* (0.397 ?0.407) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 1.73 ?1.99 (0.068 ?0.078) 0.05 ?0.21 (0.002 ?0.008) 0.65 (0.0256) bsc 0.25 ?0.38 (0.010 ?0.015) note: dimensions are in millimeters dimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * **
28 ltc2424/LTC2428 related parts part number description comments ltc1050 precision chopper stabilized op amp no external components, 5 m v offset, 1.6 m v pCp lt1236 precision bandgap reference 0.05% max initial accuracy, 5ppm/ c drift lt1461-2.5 precision, low power, low drift reference 50 m a, 0.04%, 3ppm/ c drift lt1793 low noise jfet input op amp 10pa max input bias current, low voltage noise: 8nv ltc2400 24-bit micropower ds adc in so-8 < 4ppm inl, no missing codes, 4ppm full scale ltc2404/ltc2408 4/8 channel, 24-bit ds adcs < 4ppm inl, no missing codes, interchangeable with the ltc2424/LTC2428 if zs set is grounded fiugre 25. measure dc to daylight using the LTC2428 typical applicatio n u ? linear technology corporation 2000 24248f lt/tp 0300 4k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com 24248 f25 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 9 10 11 12 13 14 15 17 + 8-channel mux 5zs set gnd 1, 6, 16, 18, 22, 27, 28 mpu serial data link microwire and spi compatable lt1236cs8-5 23 20 19, 25 21 24 csadc csmux clk d in sdo 26 f o 20-bit ? adc LTC2428 adcin muxout 7 4 3 2, 8 1 f 5v fs set v cc + out in gnd + 4 2 6 0v to 5v 100 f internal osc selected for 60hz rejection + 10 f 8v 5v ref electrometer input (ph, piezo) 5v guard ring dc voltmeter input 1mv to 1000v ?v r3, 10k 5v max c1, 0.1 f lt1793 3 2 6 4 7 + + 5v ?v ltc1050 2 3 6 7 4 r4 1k r9 1k 1% + r7 10k, 0.1% r5 5k, 1% r8 100 , 5% 3-wire r-pack r6 10k, 0.1% in914 in914 1 f ac input 60hz 60hz?f rf power r1 900k 0.1%, 1w, 1000 wvdc r2 4.7k 0.1% 50 r13 5k 0.1% 5v daylight hamamatsu photodiode s1336-5bk 100 pt rtd (3-wire) rt force sense infrared infrared thermocouple omega 0s36-01 v ref 5v 50 load bonded to rtd on insulated mounting r11 24.9k, 0.1% j1 j2 j3 v ref 5v thermistor 10k ntc local temp r12 24.9k, 0.1% r10 5k 1% 60mv to 4v 2.7v at 0 c 0.9v at 40 c 2.2mv to 16mv 0v to 4v 20mv to 80mv <1mv

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